library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dco_control is
    Port ( clk: in std_logic;
			  reset:in std_logic;
           UP : in  STD_LOGIC;
           DOWN : in  STD_LOGIC;
           DCO_CONTROL_OUT : out  STD_LOGIC_VECTOR (125 downto 0));
end dco_control;

architecture Behavioral of dco_control is
signal DCO_MID   : STD_LOGIC_VECTOR (125 downto 0):=(others => '0');

begin
process(reset,clk,UP,DOWN)

begin
	if(reset = '1') then
	--DCO_CONTROL_OUT <= (others => '0');
	DCO_MID <= "111111111111111111111111111111111" & DCO_MID(92 downto 0) ;
   else
	if(clk ='1' and clk'event) then
		if(UP = '1') then
		DCO_MID <= '1' & DCO_MID(125 downto 1);
		end if;
		
		if(DOWN = '1') then
		DCO_MID <= DCO_MID(124 downto 0) & '0';
		end if;
end if;
end if;
end process;
DCO_CONTROL_OUT <= DCO_MID;
end behavioral;
